Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
  • Introduction
  • Simulators - The Tools
  • Non-Native Simulators
  • AMCC's Race Check
  • Timing Verifiers
  • Hardware Emulators
  • Golden Simulators
  • Design Validation
  • Wafer Sort/Packages Part Sort Functional Simulation
  • Fault-Grading
  • Testability Analysis
  • Simulation Rules
  • At-Speed Simulation for Timing Verification
  • AC Tests
  • Parametric Vectors
  • Gate Tree - Any Circuit
  • Hazards
  • Structural Hazard Types
  • Functional Hazards
  • What is Required to Fix Race Problems
  • Exercises
• Case Study: Simulation
  • Introduction
  • The Schematic
    • Output Enable
    • Clock
    • MUX Enable
    • Design Checks
    • Annotation
  • The Simulations
    • Functional Simulation
    • Parametric Simulation
    • At-Speed Simulation
    • AC Test
  • Exercises
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Simulation

Last Edit July 22, 2001

Case Study: Simulation

Introduction

The following case study (the by-now-familiar 32-bit register) provides a circuit, complete with thermal diodes and a parametric gate tree. The simulation output files are formatted according to one vendor's rules and requirements. The files include the wafer sort set, at-speed, 16 AC tests (propagation path tests only) and a parametric vector set. The files pass all tests and would pass design acceptance. They are only for the maximum (military) worst-case conditions. A second set of files would be required that were produced using the minimum timing library and annotation files.

The sample step is 100 ns for all files except the at-speed file. That file must be run at the specified maximum operating frequency. Both sampled and print on change files are included per the vendor requirements.

The workstation used was a Mentor EWS on Apollo using the 1991 Q20000 Bipolar library. Identical files are produced when the design is done using a Valid or Dazix SUN system since the files are always reformatted. The formatter accepts the normal simulator output file as input and converts it into the format shown.

Fault coverage for the vector set (parametric and wafer sort taken together) is 100%. The vectors were developed using the Minimal Test Sequence methodology.

The Schematic

The circuit used to demonstrate simulation files is a 32-bit register created from the AMCC Q20000 Series macro library and was shown in the case study appendix to Chapter 3. The schematic was created using AMCC schematic rules. The overriding rule is human-readability.

Page One

Page one includes a chip macro, a pseudo-macro designed to allow the designer to communicate array-specific parameters to the design software. In this instance, the chip macro informs the software that this is a Q20080 array, using ECL interface macros in a standard -5.2V single power supply configuration. User-added parameters identify the circuit and specify that it is a military circuit. This will determine which annotation files are generated.

The library revision shows (010) - October 1990, the most current at the time of the schematic capture. The library was run under the (111) - November 1991 release. Unseen information carried by the chip macro includes number of I/O cells, number of internal cells, overhead current, switching group size and I/O macro types. Dozens of parameters are carried by the chip macro. This approach to array and circuit identification is vendor-specific.

Also shown as part of page one are a number of added power and ground macros. For TTL or TTL/ECL mixed circuits, ITPWR is a macro that will be used at placement to identify a pad that is to be tied to the +5V bus. ITGND is a macro that will be used at placement to identify a pad that is to be tied to the 0V bus. For the ECL circuits, IEVCC is used to supply either added ground (standard reference circuits) or added power (+5V reference circuits).

These macros are named since they will be placed. User-defined or instance names are used to create a placement file. They also carry a tag "AAA", which is a switching-group assignment.

The switching-group parameter is vendor-specific. It is used by AMCC software to tie simultaneously switching outputs to the added power and grounds that were added to handle them. This allows checking software to flag possible violations based on the rules issued for the specific array.

Also on page one, note the static driver.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net