Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
  • Introduction
  • Cell Types Define the Power Computation
  • DC Power in a Bipolar Array
  • DCPower in a BiCOMS Array
  • Overhead Current
  • DC Power in a CMOS Array
  • TTL Outputs - CMOS Arrays
  • ECL Static Output Power - All Arrays
  • AC Power
  • Worst-Case Power
  • Adjustment Multiplier for DC Power
  • Checking with the Vendor
  • Power Reduction Techniques
  • The Macros and Their Options
  • Macro Option Examples
  • Design Rules for Macro Options
  • Power-Down and Conditional Geometry - Bipolar
  • Terminated Outputs - Bipolar
  • Terminated Outputs - BiCMOS, CMOS
  • Inverted Outputs for Distotion Management
  • Design Rules for Power Reduction (AMCC)
  • Unused Inputs - Bipolar, BiCMOS
  • MSI and High-Functionality Macros
  • State Dependent Current - Bipolar
  • Computing DC Power Dissipation
  • Steps to Compute Maximum Worst-Case DC Power
  • Reduction for Single-Supply Circuits
  • CMOS and BiCMOS Arrays
  • Design Rules when Power is to be estimated
  • AC Macro Power Dissipation
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Power Considerations

Last Edit July 22, 2001

Computing DC Power Dissipation

Steps To Compute Maximum Worst-Case DC Power

The following example methodology assumes that typical current is specified. It applies to any power-supply configuration

• Sum all individual interface macro currents and multiply by the interface macro worst-case current multiplier. Keep IEE and ICC separate

• Sum all individual internal macro currents and multiply by the internal macro worst-case current multiplier. Keep IEE and ICC separate. Skip this step for the BiCMOS arrays

• Find the IEE and ICC overhead currents and multiply them by the worst-case overhead current multiplier. Keep IEE and ICC separate

• Add all IEE currents together

• Add all ICC currents together

• Find the worst-case VCC and VEE voltages

• Multiply IEE * VEE

• Multiply ICC * VCC

• Compute ECL static power dissipation:
  1.3 * termination current * number of outputs.
  Adjust the equation when the standard assumptions are not met

• Add all items together. This is the worst-case maximum DC power dissipated by the circuit if it is bipolar. It is the interface macro worst-case maximum DC power if the circuit is for the BiCMOS arrays

Reduction for single-supply circuits

There is an obvious reduction in the complexity of the steps if the circuit uses only one power supply. Under this condition, IEE becomes ICC when a +5V reference circuit is being analyzed. There is no ICC in a -5.2V or -4.5V single-supply circuit

Table 7-11 Currents Present By I/O Mode

The unusual dual-supply 100% ECL circuits (DECL) shown in Table 7-11 are required for minimum cell 25 ohm terminations (see the AMCC Q20000 Series Darlingtons)

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact donnamaie@sbcglobal.net