Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
  • Case Study: AMCC Design Submisison (1990)
  • Submission List Continued
  • Submission List Continued
  • Functional Simulation Submission (Required)
  • At-Speed Simulation Submiussion (Required)
  • AC Tests Path Delay Vector Submission (Optional)
  • Parametric Vectors (Required or Optional)
  • AMCC Simulation Forms - Vocabulary
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Design Submission

Last Edit September 2, 2001

At-Speed Simulation Submission (Required)

The submitted at-speed simulation is rerun after layout to verify the actual timing performance for the array. The Back-Annotation delay file, which provides the actual metal delays for the layout, is used in place of the Front-Annotation delay file. The circuit.pkg file provides package pin capacitance based on final placement to replace the estimates for package pin capacitance in the output.dly file.

At-speed simulation results provide an evaluation of the timing performance and help identify timing violations and potential timing problems. The customer must supply all at-speed simulation vectors.

AMCC requires that at-speed simulations be performed at the specified maximum operating frequency, and be performed using the minimum library and then again using the maximum worst-case library. Refer to Volume I, Section 3 for the specific series to determine which library is maximum and which minimum for the array.

The at-speed simulation, if required, should be performed following the procedures described in the design manual.

At-Speed Simulation Documentation

The documentation required for at-speed simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths, both in sampled and in print-on-change format should exist. All AMCCSUBMIT errors should be resolved prior to submission.

Documentation included on disk or tape for the sampled at-speed simulation file includes:

• the file number (1..n); no paging of at-speed files is required or necessary;
• the sampled AMCCSIMFMT file
• whether this was a MIN or MAX simulation; PRODUCT_GRADE is prompted on the form header (identifies the annotation file);
• the simulation control file name;
• the simulation input file name, if any;
• the simulation command file name which may be submit procedures, a transcript of system operation during simulation, including VIEW, RUN, START, LIST, WRITE, etc. statements as required for the specific system;
• the name of the text file version of the data or the control file which clearly describes the testing performed;
• the timing check report for the file (all simulations done for submission use timing checks active).

Documentation included on disk or tape for the print on change at-speed simulation file includes:

• everything included to document the sampled at-speed simulation except that the sampled AMCCSIMFMT file is replaced by the print on change AMCCSIMFMT file.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net