Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
  • Case Study: AMCC Design Submisison (1990)
  • Submission List Continued
  • Submission List Continued
  • Functional Simulation Submission (Required)
  • At-Speed Simulation Submiussion (Required)
  • AC Tests Path Delay Vector Submission (Optional)
  • Parametric Vectors (Required or Optional)
  • AMCC Simulation Forms - Vocabulary
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Design Submission

Last Edit MArch 18, 2002

AMCC Simulation Forms - Vocabulary

The simulation submission forms require at least one functional simulation run at worst-case maximum. The items requested are:

File # Item number, 1,2,3...

AMCCSIMFMT OUTPUT FILENAME

The user-defined name assigned to the formatted simulation output file (the vectors being submitted). The input to AMCCSIMFMT is from a VALID tabular trace output, MENTOR LIST, DAZIX VLAIF output file, etc.

MIN

Check if this is a MINIMUM simulation. This assumes a MIN timing library and FNTMIN.ews or the equivalent annotation file.

MAX

Check if this is a maximum simulation. This assumes a maximum for the product_grade timing library and FNTMIL.ews, FNTCOM.ews or the equivalent Q20000 or Q24000 annotation delay file (COM5MAXmax - fntc5mx.ews, MIL5MAXmax - fntm5mx.ews).

SIMULATION CONTROL FILENAME

The file required by the EWS to input stimulus, etc. that was used to perform the submitted simulation. It is called the SOM_MCF.SING file on DAZIX, the transcript file on MENTOR, the directives file on VALID, etc.

SIMULATION INPUT FILENAME

Any other required input file. Called the remote data VLAIF file on DAZIX, the stimulus input file on VALID. Mentor may have a data file called from the force file. The existance of this file depends on the method used to create the stimuli.

SIMULATION COMMAND FILENAME

The transcript or log of operations or submit process, i.e., what it would take for AMCC to duplicate the simulation.

AMCCVRC REPORT FILENAME

Always rename AMCCVRC.LST to a user-defined name since more than one is to be submitted. List the one that goes with the netlist and AMCCSIMFMT output file. AMCCVRC is not required for minimum simulations, for sampled at-speed simulations, or for print-on-change simulations.

AMCCVRC SIGNAL ANALYSIS FILENAME

The clock race-condition test requires a signal analysis file to specify clock-data relationships. A user-defined name.

SIMULATION DESCRIPTION FILE

The text file, may be a commented copy of the AMCCSIMFMT output file, which describes the testing being performed.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net