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Introduction
Design-Support Issues
The basic questions involving design support; which must be asked when
selecting any array include:
Which workstations are a prospective library or parts catalog available
on? What main-frame? Is the library accessible for a customer-site or
must dial-up be used?
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What error checking; at the schematic level is available? Are there
engineering rules checks (ERCs) to check on valid names, fan-out loading,
population counts, current sums, power dissipation, technology mix-ups,
array pad count, and interconnection restriction violations need to
be caught before simulation.
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What about Front-, Intermediate- and Back-Annotation;? These are
needed for metal length and load evaluation and the impact of these
on the timing. The ability of the annotation software to handle rise
and fall load factor; differences and metal layer; differences needs
to be clearly identified. Is there provision for output capacitive load
(system and package pin capacitance).
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Are there support tools; for simulation? Simulation control files,
reformatters, and vector checking; are required. Timing verifiers;
are important when path matching; is required.
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Other software that is useful for bit-slice, all arrays and any microprogrammable
architecture device is a meta-assembler;. This software allows a program
or vector set to be described in a user-defined language (a pseudo-assembler)
and compiled to ones and zeros. It provides the designer with the
ability to code the vectors in pseudo-English for readability. An
example is MICRO2 from Digital Equipment Corporation.
Also for simulation, what about automatic test generation; (ATG)?
Are design-for-test; (DFT) macros and support software available
to allow the use of this tool?
- How does placement; enter into the design sequence? This would be
board placement for components or cell placement for a semi- or full-custom
design. Does the software offer some assistance to the user in drafting
a placement file? What checking software is provided either on the workstation
or is accessible by dial-up?
Workstations, Mainframes, Dial-up
When evaluating an array library on a workstation, there must be a match
between the operating system, the graphics editor; and simulator's and
the macro library. Each installation document for a line of workstations
specifies the versions of the vendor software with which that the library
is compatible.
Check with the vendor summaries published by several technical magazines
for an initial review or check with the array vendor for a more updated
list of equipment and software compatibility.
Most array vendors offer support for several workstations. The workstations
are not restricted to semi-custom or single array design support. They
offer component libraries for board design through simulation. Multiple-array
simulations are possible if the array is correctly modeled and there is
enough memory.
Note: If you substitute software system for workstation, the rules remain pretty much the same even if we use Verilog RTL instead of schematic capture.
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