Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
  • Introduction to Chapter 1
  • Design Tools [2001]
  • Design Options
  • Semi-Custom Arrays
    
  • Selection
  • Which Array Technology?
    • Size
  • Design Support Issues
    • Schematic Rules Checking
    • Reformatters
    • Design Upgrades
  • Exercises
  • Update 2000
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Introduction

Last Edit July 22, 2001

Design-Support Issues

Schematic Rules Checking

Each workstation has a modest schematic checking pass that it makes on the way to generating the workstation-specific netlist. The error reports; from these checking routines should be checked and all pertinent errors removed. If a partial circuit is being compiled, there may be interconnect errors; that need to be ignored. The checks are not exhaustive, but later software will assume that these checking routines were successfully passed.

Workstation checks include one-ended nets, undriven page inputs, page outputs with no destination, naming confusion, missing blocks, and an attempt at duplicate name detection.

AMCC provides engineering rules checking (AMCCERC;) for commonly made schematic interconnect and design errors including too many cells for the array checked by cell type and macro type, too many fan-out loads, improper connections for 3-state and bidirectional enables, improper characters in names or too long names, improperly connected wire-ORs, dangling pins, grounded outputs, and terminated inputs. It is one of the most complete packages in the industry today.

As a part of the AMCCERC package, internal current, worst-case power dissipation for bipolar arrays, fan-out loading tables, simultaneously switching outputs reporting and power-ground checking, an I/O list, a package data list and a detailed population report are generated. Once placement is completed, these reports have a final form that becomes part of the device specification;.

Annotation

Front-Annotation; is the estimation of interconnect (pin to pin) delays in an array due to electrical fan-out loading, electrical wire-OR loading and estimated metal loading. The metal load delay estimate; is a statistical estimate based on the net size;. It is available pre-placement.

Intermediate-Annotation uses a refined estimation of the metal load delay based on the relative placement of the individual macros in an array. The electrical fan-out loads and electrical wire-OR loads remain the same. Intermediate-Annotation is generated post-placement but pre-routing.

Back-Annotation uses the final, actual metal load delay computed from the known metal lengths for the metal layers involved in the interconnect. It is available post-routing.

The availability of the annotation software, its ease of use, and the ease of integration into the simulation database is an important concern.

Output capacitive load delays; for system system capacitive load;and package pin capacitance; affect the overall path delay. The ability to specify these loads and to have their delays included in the simulation database is another item of concern. If this feature is not available, the computation must be manually performed.

Simulation Support

Every simulator has its own unique format requirements; for simulation input files. The stimulus, its switching waveform, the operating condition (military, commercial, nominal or minimum) library, sampling rates; or print on change recording, output file format, and input file format if a binary file can be read.

The workstation may offer several methods of simulation and timing verification. The vendor may only accept certain files or file formats;. List and waveform displays; are available on the three previously listed workstations. Data can be displayed in binary, octal, decimal and hex format.

Reformatters

If a standard simulation vector format; is required by the array vendor or by software to which the simulation results must be submitted as data, some means of reformatting must be available. For arrays, the functional, parametric, and AC test simulation results are generally used as input to test vector generation; software, and the allowed input formats may be restricted.

Example

AMCC accepts only binary results for specific signals (input, output, bidirectional, 3-state and bidirectional enable internal signals). Sample size is restricted. No print on change; results are used for functional simulations, only sampled. No waveforms are requested.

Since there are different simulation output formats, AMCC customers use a reformatter to translate Dazix, MENTOR, Verilog, Lasar and VALID simulation output files into a generic format;. If any other workstation is used, the output of that simulator must also be reformatted. AMCC uses their AMCCSIMFMT; software to transpose output files into an AMCC generic interface format that their test software programs can read.

Rules Checking

Regardless of the implementation selected, the design must be simulated and the parts tested. There may be a number of functional, parametric and AC test simulation vector rules; that must be followed to insure correctness in the test program. The rules are based on tester limitations;, test procedures and test objectives. The rules required by the array vendor must be clearly stated and it is increasingly desirable to have some form of rules check software available to help the designer.

AMCC supplies a vector checker, AMCCVRC;, to catch the more blatant vector rule violations such as missing required signals, too many signals switching in one vector causing noise, race conditions, undesired internal signals in the output and uneven sampling steps. Some basic toggle tests are also included.

Submission Assistance

The design submission process for custom and semi-custom arrays requires a number of specific forms, files and validation procedures be followed and the process is increasingly complex. Automation of that procedure is one desirable goal. Automation support is feasible for the I/O signal list;, package pad-pin-post, capacitive load; and I/O toggle frequency; descriptions, design validation; checklists and design submission; checklists, including simulation submission.

Placement

As a part of the submission process for custom and semi-custom arrays, the designer may wish to submit a desired placement or partial placement. The vendor must supply placement; rules and restrictions for the particular array in the selected package as well as a placement worksheet.

The user may be able to choose between a full graphic interface to the placement system or be content to supply the vendor with an ASCII list for placing some or all the macros, and let the vendor complete the placement process.

The options and the control over placement become an issue when performance is driven to the limits of the array technology. I/O placement is an issue when an array will emulate an older technology and the PC board array pin out pattern must remain unchanged.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net