Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
  • Introduction
  • Controllability
  • Observability
  • Masking a Fault
  • Fault Types
  • Fault Equivalencies
  • Single Stuck-At Faults
  • Minimal Test Sets
  • Example Test Set
  • The Problem
  • Combinatorial Circuit
  • Formation Rules for the Existence Function
  • Forming Links
  • Selecting a Chain
  • Advantages of the Test Sequence
  • Simple Gates - Sequences
  • Extension to Three-State and Bidirectional Structures
  • Extension to Sequential Circuits
  • Reference
• Case Study - 16:1 MUX D Flip/Flop Circuit
  • 100% Fault-Grade Vector Set
  • The Marquand Map
  • 2;1 MUX Example
  • 3:1 MUX Example
  • 16:1 MUX Actual Test Vectors
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Faults and Fault Detection

Last Edit July 22, 2001

3:1 MUX Example

Figure 9-16 show the Existence Function for the 3:1 MUX. To keep the map on one page, the Marquand map was broken into two halves. X5 is the output and X0-X4 are the inputs (3 data inputs and 2 select inputs).

Figure 9-16 3:1 Mux Existence Function

Figure 9-17 adds the logical-distance-1 edges. In each case, connect the two points iff (if and only if) one input changes state and one output changes state.

Figure 9-17 Adding The Links

Figure 9-18 shows one sequence in dark edges. This is for a non-clocked circuit. The actual circuit simulated used a clock output, doubling the size of the vector set (change data in one step, change the clock in the next).

Figure 9-18 Identifying The Sequence

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
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