Bit-Slice Design: Controllers and ALUs

Refining the CCU

Last Edit November 2, 1996; May 1, 1999; July 7, 2001

Am2910 Instructions

COND JSB R/PL (JSRP)

Subroutines may also be called by the Conditional Jump Subroutine from Register or Pipeline, which should have been given the mnemonic CSRP. The instruction is similar to JRP except that regardless of the test result, the next sequential address (54 in Figure 4-17) is pushed onto the stack and the TOS pointer is incremented. As with JRP, LDCT (or its equivalent operation) must have occurred prior to the execution of JSRP.

Figure 4-17 Conditional jump subroutine register/pipeline (JSRP, 5, 0101).
LDCT or a register load must occur somewhere prior to JSRP

If CC' is LOW, a branch is taken to the subroutine whose address is taken from the register/counter (70 in the figure). The PL' enable is ACTIVE, and the register/counter and the stack are unaffected. If CC' is HIGH, the start address is taken from the branch address field (80 in the figure).

COND Return (CRTN)

Once a subroutine has been completed, an unconditional return to the calling program is accomplished using a Conditional Return Statement. The same statement is also used to conditionally end a subroutine based on the result of a test.

There are two ways to allow an unconditional return -- either the selcted input to the conditional MUX is a forced PASS input (grounded in the active-LOW case), or the CCEN' input is switched HIGH. CCEN' will be discussed later. If CC' is LOW either as a result of a valid test or frm a forced LOW input, the next address is taken from the LIFO stack and the stack is POPed (the TOS pointer is decremented). The register/counter is unaffected, and the PL' enable is ACTIVE.

If CC' is HIGH, CRTN behaves as CONT. In either case, CRTN should not be executed if the stack is empty (see Figure 4-18).

Figure 4-18 Conditional Return (CRTN, A, 1010)

Repeat PL CNTR ≠ 0 (RPCT)

Loops are handled with four different instructions. One of these is RPCT, the Repeat Loop instruction, with the start address of the loop in the pipeline register. Essentially, it is a conditional jump pipeline instruction. The register/counter must have been loaded previously via a LDCT or equivalent operation.

If the counter is ≠ 0 (zero), the jump is taken and the counter is decremented. If <COUNTER> = 0, then RPCT behaves as CONT. The stack is unaffected, and the PL' enable is active (see Figure 4-19).

Figure 4-19 Repeat pipeline if counter not = 0 (RPCT, 9, 1001). (Loop on one or more statements, beginning address of loop in register (at the time of the RPCT statement).

Push/COND LD CNTR (PUSH)

The counter can be conditionally loaded during the same instruction that pushes the current value of the µPC register onto the LIFO stack. If CC' is LOW, the counter is loaded from the pipeline register. If CC' is HIGH. the register/counter is unchanged. The PUSH occurs regardless of the CC' input value. The PL enable is active (see Figure 4-20).

PUSH must immediately precede the first microinstruction in a loop controlled by LOOP, RFCT, or TWB.

Figure 4-20 Push stack and condition load counter (PUSH, 4, 1000). This instruction must immediately precede the first statement in a loop controlled by LOOP or RFCT.

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